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base:classic_hard-restart_and_about_adsr_in_generally [2017-04-28 22:49] – [What is ADSR-Bug?] mixerbase:classic_hard-restart_and_about_adsr_in_generally [2017-04-30 21:50] (current) – Added credits in the article itself (too). ftc
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 ====== ADSR Discussion Notes====== ====== ADSR Discussion Notes======
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 +By mixer with contributions from many.
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 Few notes about what has been discussed about SID envelopes lately at CSDB and at IRC. Errors are all mine, and this being a Wiki, you can fix them. :) This text could use some generic bits about ADSR and code-examples. Few notes about what has been discussed about SID envelopes lately at CSDB and at IRC. Errors are all mine, and this being a Wiki, you can fix them. :) This text could use some generic bits about ADSR and code-examples.
  
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 SID volume-envelope aka. ADSR has a 15-bit LFSR that acts as a prescaler to ENV counter. This LFSR determines the rate at which ENV counter is advanced. The register value of A,D or R corresponds to a number in a hardcoded table within SID chip. Number in the table is the LFSR comparison value to which LFSR state is compared. LFSR advances every clock cycle. When LFSR state equals to the comparison value, LFSR is set to its start value and ENV counter is advanced. ADSR bug occurs, when A,D or R values are changed when the LFSR has already passed the corresponding new comparison value. The LFSR must then run a full cycle before the new comparison value can be reached. Full cycle takes 32768 cycles. That is 1.7 frames in terms of 1/50 fps frames  SID volume-envelope aka. ADSR has a 15-bit LFSR that acts as a prescaler to ENV counter. This LFSR determines the rate at which ENV counter is advanced. The register value of A,D or R corresponds to a number in a hardcoded table within SID chip. Number in the table is the LFSR comparison value to which LFSR state is compared. LFSR advances every clock cycle. When LFSR state equals to the comparison value, LFSR is set to its start value and ENV counter is advanced. ADSR bug occurs, when A,D or R values are changed when the LFSR has already passed the corresponding new comparison value. The LFSR must then run a full cycle before the new comparison value can be reached. Full cycle takes 32768 cycles. That is 1.7 frames in terms of 1/50 fps frames 
  
-Another way to think of the LFSR is that it is the inner loop within another loop and the problem is that inner loop comparison value can be changed at any moment. If the inner loop comparison value is 60 and loop has already done 50 repeats and someone sets new comparison value to 30, the inner loop will run through its repeat counter until it restarts. EDITED: it was pointed out to me that the analogue of inner loop is wrong. However, the analogue of a loop comparison value being changed, so that the comparison is not met, is still apt.+Another way to think of the LFSR is that it is the inner loop within another loop and the problem is that inner loop comparison value can be changed at any moment. If the inner loop comparison value is 60 and loop has already done 50 repeats and someone sets new comparison value to 30, the inner loop will run through its repeat counter until it restarts. EDITED: it was pointed out to me that the analogue of inner loop is wrong. However, the analogue of a loop comparison value being changed, so that the comparison value is not met, is still apt.
  
 All cases where one puts lower than previous value to A,D or R registers can cause the bug conditon. Also gate on/gate off can switch between ADSR states A,DS->R or R->A so that the change takes place from larger value to smaller value. Equal or larger values for A,D or R are safe. All cases where one puts lower than previous value to A,D or R registers can cause the bug conditon. Also gate on/gate off can switch between ADSR states A,DS->R or R->A so that the change takes place from larger value to smaller value. Equal or larger values for A,D or R are safe.
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 Often registers are written in the order: AD, SR, Control register. Each of the writes can trigger the bug, there is no way around it, but, now we know which ADSR writes or state changes have chance of causing the bug. Often registers are written in the order: AD, SR, Control register. Each of the writes can trigger the bug, there is no way around it, but, now we know which ADSR writes or state changes have chance of causing the bug.
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base/classic_hard-restart_and_about_adsr_in_generally.1493412592.txt.gz · Last modified: 2017-04-28 22:49 by mixer