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+ | ====== Extra Instructions Of The 65XX Series CPU ====== | ||
+ | < | ||
+ | By: Adam Vardy (abe0084@infonet.st-johns.nf.ca) | ||
+ | |||
+ | [File created: 22, Aug. 1995... 27, Sept. 1996] | ||
+ | |||
+ | The following is a list of 65XX/85XX extra opcodes. | ||
+ | for the 6502 CPU fit in a single byte; out of 256 possible combinations, | ||
+ | only 151 are " | ||
+ | codes. | ||
+ | instruction set. They are also referred to as undefined opcodes or | ||
+ | undocumented opcodes or non-standard opcodes or unofficial opcodes. | ||
+ | "The Commodore 64 Programmer' | ||
+ | are simply marked as future expansion. | ||
+ | with help from "The Complete Inner Space Anthology" | ||
+ | |||
+ | I have marked off the beginning of the description of each opcode with a | ||
+ | few asterisks. | ||
+ | All opcode values are given in hexadecimal. | ||
+ | listed immediately to the right of any sample code. The lowercase letters | ||
+ | found in these examples represent the hex digits that you must provide as | ||
+ | the instruction' | ||
+ | or source address. | ||
+ | referred to as ' | ||
+ | absolute address are referred to as ' | ||
+ | |||
+ | Execution times for all opcodes are given alongside to the very right of | ||
+ | any sample code. A number of the opcodes described here combine the | ||
+ | operation of two regular 6502 instructions. | ||
+ | 6502 instruction set for more information, | ||
+ | instruction affects. | ||
+ | </ | ||
+ | ====== ASO *** (SLO) ====== | ||
+ | < | ||
+ | This opcode ASLs the contents of a memory location and then ORs the result | ||
+ | with the accumulator. | ||
+ | |||
+ | Supported modes: | ||
+ | |||
+ | ASO abcd ;0F cd ab ;No. Cycles= 6 | ||
+ | ASO abcd, | ||
+ | ASO abcd, | ||
+ | ASO ab ;07 ab ; | ||
+ | ASO ab,X ;17 ab ; | ||
+ | ASO (ab, | ||
+ | ASO (ab), | ||
+ | |||
+ | (Sub-instructions: | ||
+ | |||
+ | Here is an example of how you might use this opcode: | ||
+ | |||
+ | ASO $C010 ;0F 10 C0 | ||
+ | |||
+ | Here is the same code using equivalent instructions. | ||
+ | |||
+ | ASL $C010 | ||
+ | ORA $C010 | ||
+ | </ | ||
+ | ====== RLA *** ====== | ||
+ | < | ||
+ | RLA ROLs the contents of a memory location and then ANDs the result with | ||
+ | the accumulator. | ||
+ | |||
+ | Supported modes: | ||
+ | |||
+ | RLA abcd ;2F cd ab ;No. Cycles= 6 | ||
+ | RLA abcd, | ||
+ | RLA abcd, | ||
+ | RLA ab ;27 ab ; | ||
+ | RLA ab,X ;37 ab ; | ||
+ | RLA (ab, | ||
+ | RLA (ab), | ||
+ | |||
+ | (Sub-instructions: | ||
+ | |||
+ | Here's an example of how you might write it in a program. | ||
+ | |||
+ | RLA $FC,X ;37 FC | ||
+ | |||
+ | Here's the same code using equivalent instructions. | ||
+ | |||
+ | ROL $FC,X | ||
+ | AND $FC,X | ||
+ | </ | ||
+ | ====== LSE *** (SRE) ====== | ||
+ | < | ||
+ | LSE LSRs the contents of a memory location and then EORs the result with | ||
+ | the accumulator. | ||
+ | |||
+ | Supported modes: | ||
+ | |||
+ | LSE abcd ;4F cd ab ;No. Cycles= 6 | ||
+ | LSE abcd, | ||
+ | LSE abcd, | ||
+ | LSE ab ;47 ab ; | ||
+ | LSE ab,X ;57 ab ; | ||
+ | LSE (ab, | ||
+ | LSE (ab), | ||
+ | |||
+ | (Sub-instructions: | ||
+ | |||
+ | Example: | ||
+ | |||
+ | LSE $C100, | ||
+ | |||
+ | Here's the same code using equivalent instructions. | ||
+ | |||
+ | LSR $C100,X | ||
+ | EOR $C100,X | ||
+ | </ | ||
+ | ====== RRA *** ====== | ||
+ | < | ||
+ | RRA RORs the contents of a memory location and then ADCs the result with | ||
+ | the accumulator. | ||
+ | |||
+ | Supported modes: | ||
+ | |||
+ | RRA abcd ;6F cd ab ;No. Cycles= 6 | ||
+ | RRA abcd, | ||
+ | RRA abcd, | ||
+ | RRA ab ;67 ab ; | ||
+ | RRA ab,X ;77 ab ; | ||
+ | RRA (ab, | ||
+ | RRA (ab), | ||
+ | |||
+ | (Sub-instructions: | ||
+ | |||
+ | Example: | ||
+ | |||
+ | RRA $030C ;6F 0C 03 | ||
+ | |||
+ | Equivalent instructions: | ||
+ | |||
+ | ROR $030C | ||
+ | ADC $030C | ||
+ | </ | ||
+ | ====== AXS *** (SAX) ====== | ||
+ | < | ||
+ | AXS ANDs the contents of the A and X registers (without changing the | ||
+ | contents of either register) and stores the result in memory. | ||
+ | AXS does not affect any flags in the processor status register. | ||
+ | |||
+ | Supported modes: | ||
+ | |||
+ | AXS abcd ;8F cd ab ;No. Cycles= 4 | ||
+ | AXS ab ;87 ab ; | ||
+ | AXS ab,Y ;97 ab ; | ||
+ | AXS (ab, | ||
+ | |||
+ | (Sub-instructions: | ||
+ | |||
+ | Example: | ||
+ | |||
+ | AXS $FE ;87 FE | ||
+ | |||
+ | Here's the same code using equivalent instructions. | ||
+ | |||
+ | STX $FE | ||
+ | PHA | ||
+ | AND $FE | ||
+ | STA $FE | ||
+ | PLA | ||
+ | </ | ||
+ | ====== LAX *** ====== | ||
+ | < | ||
+ | This opcode loads both the accumulator and the X register with the contents | ||
+ | of a memory location. | ||
+ | |||
+ | Supported modes: | ||
+ | |||
+ | LAX abcd ;AF cd ab ;No. Cycles= 4 | ||
+ | LAX abcd, | ||
+ | LAX ab ;A7 ab ; | ||
+ | LAX ab,Y ;B7 ab ;if page 4 | ||
+ | LAX (ab, | ||
+ | LAX (ab), | ||
+ | |||
+ | (Sub-instructions: | ||
+ | |||
+ | Example: | ||
+ | |||
+ | LAX $8400, | ||
+ | |||
+ | Equivalent instructions: | ||
+ | |||
+ | LDA $8400,Y | ||
+ | LDX $8400,Y | ||
+ | </ | ||
+ | ====== DCM *** (DCP) ====== | ||
+ | < | ||
+ | This opcode DECs the contents of a memory location and then CMPs the result | ||
+ | with the A register. | ||
+ | |||
+ | Supported modes: | ||
+ | |||
+ | DCM abcd ;CF cd ab ;No. Cycles= 6 | ||
+ | DCM abcd, | ||
+ | DCM abcd, | ||
+ | DCM ab ;C7 ab ; | ||
+ | DCM ab,X ;D7 ab ; | ||
+ | DCM (ab, | ||
+ | DCM (ab), | ||
+ | |||
+ | (Sub-instructions: | ||
+ | |||
+ | Example: | ||
+ | |||
+ | DCM $FF ;C7 FF | ||
+ | |||
+ | Equivalent instructions: | ||
+ | |||
+ | DEC $FF | ||
+ | CMP $FF | ||
+ | </ | ||
+ | ====== INS *** (ISC) ====== | ||
+ | < | ||
+ | This opcode INCs the contents of a memory location and then SBCs the result | ||
+ | from the A register. | ||
+ | |||
+ | Supported modes: | ||
+ | |||
+ | INS abcd ;EF cd ab ;No. Cycles= 6 | ||
+ | INS abcd, | ||
+ | INS abcd, | ||
+ | INS ab ;E7 ab ; | ||
+ | INS ab,X ;F7 ab ; | ||
+ | INS (ab, | ||
+ | INS (ab), | ||
+ | |||
+ | (Sub-instructions: | ||
+ | |||
+ | Example: | ||
+ | |||
+ | INS $FF ;E7 FF | ||
+ | |||
+ | Equivalent instructions: | ||
+ | |||
+ | INC $FF | ||
+ | SBC $FF | ||
+ | </ | ||
+ | ====== ALR *** ====== | ||
+ | < | ||
+ | This opcode ANDs the contents of the A register with an immediate value and | ||
+ | then LSRs the result. | ||
+ | |||
+ | One supported mode: | ||
+ | |||
+ | ALR #ab ;4B ab ;No. Cycles= 2 | ||
+ | |||
+ | Example: | ||
+ | |||
+ | ALR #$FE ;4B FE | ||
+ | |||
+ | Equivalent instructions: | ||
+ | |||
+ | AND #$FE | ||
+ | LSR A | ||
+ | </ | ||
+ | ====== ARR *** ====== | ||
+ | < | ||
+ | This opcode ANDs the contents of the A register with an immediate value and | ||
+ | then RORs the result. | ||
+ | |||
+ | One supported mode: | ||
+ | |||
+ | ARR #ab ;6B ab ;No. Cycles= 2 | ||
+ | |||
+ | Here's an example of how you might write it in a program. | ||
+ | |||
+ | ARR #$7F ;6B 7F | ||
+ | |||
+ | Here's the same code using equivalent instructions. | ||
+ | |||
+ | AND #$7F | ||
+ | ROR A | ||
+ | </ | ||
+ | ====== XAA *** ====== | ||
+ | < | ||
+ | XAA transfers the contents of the X register to the A register and then | ||
+ | ANDs the A register with an immediate value. | ||
+ | |||
+ | One supported mode: | ||
+ | |||
+ | XAA #ab ;8B ab ;No. Cycles= 2 | ||
+ | |||
+ | Example: | ||
+ | |||
+ | XAA #$44 ;8B 44 | ||
+ | |||
+ | Equivalent instructions: | ||
+ | |||
+ | TXA | ||
+ | AND #$44 | ||
+ | </ | ||
+ | ====== OAL *** ====== | ||
+ | < | ||
+ | This opcode ORs the A register with #$EE, ANDs the result with an immediate | ||
+ | value, and then stores the result in both A and X. | ||
+ | |||
+ | One supported mode: | ||
+ | |||
+ | OAL #ab ;AB ab ;No. Cycles= 2 | ||
+ | |||
+ | Here's an example of how you might use this opcode: | ||
+ | |||
+ | OAL #$AA ;AB AA | ||
+ | |||
+ | Here's the same code using equivalent instructions: | ||
+ | |||
+ | ORA #$EE | ||
+ | AND #$AA | ||
+ | TAX | ||
+ | </ | ||
+ | ====== SAX *** ====== | ||
+ | < | ||
+ | SAX ANDs the contents of the A and X registers (leaving the contents of A | ||
+ | intact), subtracts an immediate value, and then stores the result in X. | ||
+ | ... A few points might be made about the action of subtracting an immediate | ||
+ | value. | ||
+ | does not store the result of the subtraction it performs in any register. | ||
+ | This subtract operation is not affected by the state of the Carry flag, | ||
+ | though it does affect the Carry flag. It does not affect the Overflow | ||
+ | flag. | ||
+ | |||
+ | One supported mode: | ||
+ | |||
+ | SAX #ab ;CB ab ;No. Cycles= 2 | ||
+ | |||
+ | Example: | ||
+ | |||
+ | SAX #$5A ;CB 5A | ||
+ | |||
+ | Equivalent instructions: | ||
+ | |||
+ | STA $02 | ||
+ | TXA | ||
+ | AND $02 | ||
+ | SEC | ||
+ | SBC #$5A | ||
+ | TAX | ||
+ | LDA $02 | ||
+ | |||
+ | Note: Memory location $02 would not be altered by the SAX opcode. | ||
+ | </ | ||
+ | ====== NOP *** ====== | ||
+ | < | ||
+ | NOP performs no operation. | ||
+ | Takes 2 cycles to execute. | ||
+ | </ | ||
+ | ====== SKB *** ====== | ||
+ | < | ||
+ | SKB stands for skip next byte. | ||
+ | Opcodes: 80, 82, C2, E2, 04, 14, 34, 44, 54, 64, 74, D4, F4. | ||
+ | Takes 2, 3, or 4 cycles to execute. | ||
+ | </ | ||
+ | ====== SKW *** ====== | ||
+ | < | ||
+ | SKW skips next word (two bytes). | ||
+ | Opcodes: 0C, 1C, 3C, 5C, 7C, DC, FC. | ||
+ | Takes 4 cycles to execute. | ||
+ | |||
+ | To be dizzyingly precise, SKW actually performs a read operation. | ||
+ | just that the value read is not stored in any register. | ||
+ | uses the absolute addressing mode. The two bytes which follow it form the | ||
+ | absolute address. | ||
+ | addressing mode. If a page boundary is crossed, the execution time of one | ||
+ | of these SKW opcodes is upped to 5 clock cycles. | ||
+ | -------------------------------------------------------------------------- | ||
+ | |||
+ | The following opcodes were discovered and named exclusively by the author. | ||
+ | (Or so it was thought before.) | ||
+ | </ | ||
+ | ====== HLT *** ====== | ||
+ | < | ||
+ | HLT crashes the microprocessor. | ||
+ | execution ceases. | ||
+ | has characterized this instruction as a halt instruction since this is the | ||
+ | most straightforward explanation for this opcode' | ||
+ | will restart execution. | ||
+ | performed! | ||
+ | |||
+ | Opcodes: 02, 12, 22, 32, 42, 52, 62, 72, 92, B2, D2, F2. | ||
+ | </ | ||
+ | ====== TAS *** ====== | ||
+ | < | ||
+ | This opcode ANDs the contents of the A and X registers (without changing | ||
+ | the contents of either register) and transfers the result to the stack | ||
+ | pointer. | ||
+ | the target address of the operand +1 and stores that final result in | ||
+ | memory. | ||
+ | |||
+ | One supported mode: | ||
+ | |||
+ | TAS abcd, | ||
+ | |||
+ | (Sub-instructions: | ||
+ | |||
+ | Here is an example of how you might use this opcode: | ||
+ | |||
+ | TAS $7700, | ||
+ | |||
+ | Here is the same code using equivalent instructions. | ||
+ | |||
+ | STX $02 | ||
+ | STA $FB | ||
+ | AND $02 | ||
+ | TAX | ||
+ | TXS | ||
+ | AND #$78 | ||
+ | STA $7700,Y | ||
+ | LDA $FB | ||
+ | LDX $02 | ||
+ | |||
+ | Note: Memory locations $02 and $FB would not be altered by the TAS opcode. | ||
+ | |||
+ | Above I used the phrase 'the high byte of the target address of the operand | ||
+ | +1' | ||
+ | specified explicitly in the operand. | ||
+ | after the opcode (ab). So we'll shorten that phrase to AB+1. | ||
+ | </ | ||
+ | ====== SAY *** ====== | ||
+ | < | ||
+ | This opcode ANDs the contents of the Y register with < | ||
+ | result in memory. | ||
+ | |||
+ | One supported mode: | ||
+ | |||
+ | SAY abcd, | ||
+ | |||
+ | Example: | ||
+ | |||
+ | SAY $7700, | ||
+ | |||
+ | Equivalent instructions: | ||
+ | |||
+ | PHA | ||
+ | TYA | ||
+ | AND #$78 | ||
+ | STA $7700,X | ||
+ | PLA | ||
+ | </ | ||
+ | ====== XAS *** ====== | ||
+ | < | ||
+ | This opcode ANDs the contents of the X register with < | ||
+ | result in memory. | ||
+ | |||
+ | One supported mode: | ||
+ | |||
+ | XAS abcd, | ||
+ | |||
+ | Example: | ||
+ | |||
+ | XAS $6430, | ||
+ | |||
+ | Equivalent instructions: | ||
+ | |||
+ | PHA | ||
+ | TXA | ||
+ | AND #$65 | ||
+ | STA $6430,Y | ||
+ | PLA | ||
+ | </ | ||
+ | ====== AXA *** ====== | ||
+ | < | ||
+ | This opcode stores the result of A AND X AND the high byte of the target | ||
+ | address of the operand +1 in memory. | ||
+ | |||
+ | Supported modes: | ||
+ | |||
+ | AXA abcd, | ||
+ | AXA (ab), | ||
+ | |||
+ | Example: | ||
+ | |||
+ | AXA $7133, | ||
+ | |||
+ | Equivalent instructions: | ||
+ | |||
+ | STX $02 | ||
+ | PHA | ||
+ | AND $02 | ||
+ | AND #$72 | ||
+ | STA $7133,Y | ||
+ | PLA | ||
+ | LDX $02 | ||
+ | |||
+ | Note: Memory location $02 would not be altered by the AXA opcode. | ||
+ | |||
+ | |||
+ | The following notes apply to the above four opcodes: TAS, SAY, XAS, AXA. | ||
+ | |||
+ | None of these opcodes affect the accumulator, | ||
+ | register, or the processor status register! | ||
+ | The author has no explanation for the complexity of these | ||
+ | instructions. | ||
+ | the convoluted sequence of events which appears to occur while executing | ||
+ | one of these opcodes. | ||
+ | these instructions appear to be corruptions of other instructions. | ||
+ | example, the opcode SAY would have been one of the addressing modes of the | ||
+ | standard instruction STY (absolute indexed X) were it not for the fact that | ||
+ | the normal operation of this instruction is impaired in this particular | ||
+ | instance. | ||
+ | |||
+ | One irregularity uncovered is that sometimes the actual value is stored in | ||
+ | memory, and the AND with < | ||
+ | This happens very infrequently. | ||
+ | the video display. | ||
+ | screen is blanked or C128 2MHz mode is enabled. | ||
+ | |||
+ | --- Imported example --- | ||
+ | Here is a demo program to illustrate the above effect. | ||
+ | There is no exit, so you'll have to hit Stop-Restore to quit. And you may | ||
+ | want to clear the screen before running it. For contrast, there is a | ||
+ | second routine which runs during idle state display. | ||
+ | After trying the second routine, check it out again using POKE 53269,255 to | ||
+ | enable sprites. | ||
+ | |||
+ | begin 640 say->sty | ||
+ | D""" | ||
+ | ` | ||
+ | end | ||
+ | |||
+ | --- Text import end --- | ||
+ | |||
+ | WARNING: If the target address crosses a page boundary because of indexing, | ||
+ | the instruction may not store at the intended address. | ||
+ | storing in zero page, or another address altogether (page=value stored). | ||
+ | Apparently certain internal 65XX registers are being overridden. | ||
+ | scheme behind this erratic behaviour is very complex and strange. | ||
+ | |||
+ | |||
+ | And continuing with the list... | ||
+ | </ | ||
+ | ====== ANC *** ====== | ||
+ | < | ||
+ | ANC ANDs the contents of the A register with an immediate value and then | ||
+ | moves bit 7 of A into the Carry flag. This opcode works basically | ||
+ | identically to AND #immed. except that the Carry flag is set to the same | ||
+ | state that the Negative flag is set to. | ||
+ | |||
+ | One supported mode: | ||
+ | |||
+ | ANC #ab ;2B ab ;No. Cycles= 2 | ||
+ | ANC #ab ;0B ab | ||
+ | |||
+ | (Sub-instructions: | ||
+ | |||
+ | OPCODE 89 | ||
+ | Opcode 89 is another SKB instruction. | ||
+ | </ | ||
+ | ====== LAS *** ====== | ||
+ | < | ||
+ | This opcode ANDs the contents of a memory location with the contents of the | ||
+ | stack pointer register and stores the result in the accumulator, | ||
+ | register, and the stack pointer. | ||
+ | |||
+ | One supported mode: | ||
+ | |||
+ | LAS abcd, | ||
+ | |||
+ | OPCODE EB | ||
+ | Opcode EB seems to work exactly like SBC # | ||
+ | </ | ||
+ | ====== That is the end of the list. ====== | ||
+ | < | ||
+ | This list is a full and complete list of all undocumented opcodes, every | ||
+ | last hex value. | ||
+ | corrects some incorrect information found elsewhere. | ||
+ | MKX (also known as TSTA and TSTX) as described in "The Complete Commodore | ||
+ | Inner Space Anthology" | ||
+ | there that the instructions ASO, RLA, LSE, RRA have an immediate addressing | ||
+ | mode. (RLA #ab would be ANC #ab.) | ||
+ | </ | ||
+ | ====== [Recent additions to this text file] ====== | ||
+ | < | ||
+ | Here are some other more scrutinizing observations. | ||
+ | |||
+ | The opcode ARR operates more complexily than actually described in the list | ||
+ | above. | ||
+ | flag is clear. | ||
+ | ($69), not AND. While ADC is not performed, some of the ADC mechanics are | ||
+ | evident. | ||
+ | occur after ANDing but before RORing. | ||
+ | exclusive ORing bit 7 with bit 6. Unlike ROR, bit 0 does not go into the | ||
+ | carry flag. The state of bit 7 is exchanged with the carry flag. Bit 0 is | ||
+ | lost. All of this may appear strange, but it makes sense if you consider | ||
+ | the probable internal operations of ADC itself. | ||
+ | |||
+ | SKB opcodes 82, C2, E2 may be HLTs. Since only one source claims this, and | ||
+ | no other sources corroborate this, it must be true on very few machines. | ||
+ | On all others, these opcodes always perform no operation. | ||
+ | |||
+ | LAS is suspect. | ||
+ | |||
+ | OPCODE BIT-PATTERN: | ||
+ | Now it is time to discuss XAA ($8B) and OAL ($AB). | ||
+ | controversy has surrounded these two opcodes. | ||
+ | for this. 1 - They are rather weird in operation. | ||
+ | differently on different machines. | ||
+ | |||
+ | Here is the basic operation. | ||
+ | OAL | ||
+ | This opcode ORs the A register with #xx, ANDs the result with an immediate | ||
+ | value, and then stores the result in both A and X. | ||
+ | |||
+ | On my 128, xx may be EE,EF,FE, OR FF. These possibilities appear to depend | ||
+ | on three factors: the X register, PC, and the previous instruction | ||
+ | executed. | ||
+ | this opcode appears to work exactly as described in the list. | ||
+ | |||
+ | On my 64, OAL produces all sorts of values for xx: 00, | ||
+ | rough scenario I worked out to explain this is here. The constant value EE | ||
+ | disappears entirely. | ||
+ | with certain bits of X and also ORed with certain bits of another | ||
+ | " | ||
+ | However, if OAL is preceded by certain other instructions like NOP, the | ||
+ | constant value EE reappears and the foregoing does not take place. | ||
+ | |||
+ | On my 64, XAA works like this. While X is transfered to A, bit 0 and bit 4 | ||
+ | are not. Instead, these bits are ANDed with those bits from A, and the | ||
+ | result is stored in A. | ||
+ | |||
+ | There may be many variations in the behaviour of both opcodes. | ||
+ | OAL #$00 are likely quite reliable in any case. It seems clear that the | ||
+ | video chip (i.e., VIC-II) bears responsibility for some small part of the | ||
+ | anomalousness, | ||
+ | |||
+ | One idea I'll just throw up in the air about why the two opcodes behave as | ||
+ | they do is this observation. | ||
+ | AND as their first step, 8B and AB do not. Perhaps this difference leads | ||
+ | to some internal conflict in the microprocessor. | ||
+ | " | ||
+ | |||
+ | All of the opcodes in this list (at least up to the dividing line) use the | ||
+ | naming convention from the CCISA Anthology book. There is another naming | ||
+ | convention used, for example in the first issue of C=Hacking. | ||
+ | assembler I know of that supports undocumented opcodes is Power Assembler. | ||
+ | And it uses the same naming conventions as used here. | ||
+ | |||
+ | One note on a different topic. | ||
+ | 64 Programmers Reference Guide with the instruction set listing. | ||
+ | last row, in the last column of the two instructions AND and ORA there | ||
+ | should be an asterisk, just as there is with ADC. That is the indirect, | ||
+ | addressing mode. In another table several pages later correct information | ||
+ | is given. | ||
+ | |||
+ | (A correction: | ||
+ | addressing mode for LAX was given as LAX ab,X. This should have been | ||
+ | LAX ab,Y (B7). Also note that Power Assembler apparently has this same | ||
+ | error, likely because both it and this document derive first from the same | ||
+ | source as regards these opcodes. | ||
+ | produces the output B7 00.) | ||
+ | </ | ||
+ | ====== References ====== | ||
+ | * Joel Shepherd. "Extra Instructions" | ||
+ | * Jim Butterfield. " | ||
+ | * Raymond Quirling. "6510 Opcodes" | ||
+ | * John West, Marko Mäkelä. ' | ||
base/extra_instructions_of_the_65xx_series_cpu.txt · Last modified: 2015-04-17 04:31 by 127.0.0.1